PIC18 LaurTec Library  3.2.0
Open Source C Library for PIC18 Microcontrollers based on C18 - XC8 Compilers
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PIC18F4550_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.0
5 Created on Date : 02/02/2013
6 Last update : 29/09/2013
7 
8 CopyRight 2006-2013 all rights are reserved
9 
10 ********************************************************
11 SOFTWARE LICENSE AGREEMENT
12 ********************************************************
13 
14 The usage of the supplied software imply the acceptance of the following license.
15 
16 The software supplied herewith by Mauro Laurenti (the Author)
17 is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
18 The software is owned by the Author, and is protected under applicable copyright laws.
19 All rights are reserved.
20 Any use in violation of the foregoing restrictions may subject the
21 user to criminal sanctions under applicable laws (Italian or International ones), as well as to
22 civil liability for the breach of the terms and conditions of this license.
23 Commercial use is forbidden without a written acknowledgement with the Author.
24 Personal or educational use is allowed if the application containing the following
25 software doesn't aim to commercial use or monetary earning of any kind.
26 
27 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
28 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
29 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
30 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
31 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
32 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
33 
34 ********************************************************
35 PURPOSES
36 ********************************************************
37 
38 This file contains all the configuration words needed for the PIC18F4550.
39 It can be easily adapted to other PICs according to the available configurations.
40 
41 ****** WARNING ******
42 
43 The configurations must be changed to reflect the application needs!
44 
45 *******************************************************************************/
46 
47 
48 #ifndef PIC18F4550_CONFIG_H
49 #define PIC18F4550_CONFIG_H
50 
51 #ifdef __XC8
52 #include <xc.h>
53 #endif
54 
55 //******************************************************************************
56 // Register: CONFIG1L @ 0x300000
57 //******************************************************************************
58 
59 // System Clock Postscaler Selection bits
60 //OSC2_PLL3 [Primary Oscillator Src: /2][96 MHz PLL Src: /3]
61 //OSC4_PLL6 [Primary Oscillator Src: /4][96 MHz PLL Src: /6]
62 //OSC3_PLL4 [Primary Oscillator Src: /3][96 MHz PLL Src: /4]
63 //OSC1_PLL2 [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
64 #pragma config CPUDIV = OSC1_PLL2
65 
66 //PLL Prescaler Selection bits
67 //1 No prescale (4 MHz oscillator input drives PLL directly)
68 //5 Divide by 5 (20 MHz oscillator input)
69 //12 Divide by 12 (48 MHz oscillator input)
70 //2 Divide by 2 (8 MHz oscillator input)
71 //6 Divide by 6 (24 MHz oscillator input)
72 //3 Divide by 3 (12 MHz oscillator input)
73 //10 Divide by 10 (40 MHz oscillator input)
74 //4 Divide by 4 (16 MHz oscillator input)
75 #pragma config PLLDIV = 1
76 
77 //USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
78 //1 USB clock source comes directly from the primary oscillator block with no postscale
79 //2 USB clock source comes from the 96 MHz PLL divided by 2
80 #pragma config USBDIV = 2
81 
82 
83 //******************************************************************************
84 // Register: CONFIG1H @ 0x300001
85 //******************************************************************************
86 
87 //Internal/External Oscillator Switchover bit
88 //OFF Oscillator Switchover mode disabled
89 //ON Oscillator Switchover mode enabled
90 #pragma config IESO = OFF
91 
92 //Oscillator Selection bits
93 //INTOSC_EC Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
94 //ECPLLIO_EC EC oscillator, PLL enabled, port function on RA6 (ECPIO)
95 //XT_XT XT oscillator (XT)
96 //INTOSC_HS Internal oscillator, HS oscillator used by USB (INTHS)
97 //ECPLL_EC EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
98 //INTOSC_XT Internal oscillator, XT used by USB (INTXT)
99 //EC_EC EC oscillator, CLKO function on RA6 (EC)
100 //ECIO_EC EC oscillator, port function on RA6 (ECIO)
101 //XTPLL_XT XT oscillator, PLL enabled (XTPLL)
102 //HSPLL_HS HS oscillator, PLL enabled (HSPLL)
103 //HS HS oscillator (HS)
104 //INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB (INTIO)
105 #pragma config FOSC = HS
106 
107 //Fail-Safe Clock Monitor Enable bit
108 //OFF Fail-Safe Clock Monitor disabled
109 //ON Fail-Safe Clock Monitor enabled
110 
111 #pragma config FCMEN = OFF
112 
113 //******************************************************************************
114 // Register: CONFIG2L @ 0x300002
115 //******************************************************************************
116 
118 //OFF USB voltage regulator disabled
119 //ON USB voltage regulator enabled
120 #pragma config VREGEN = OFF
121 
122 //Brown-out Reset Enable bits
123 //SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
124 //OFF Brown-out Reset disabled in hardware and software
125 //ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
126 //ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
127 #pragma config BOR = OFF
128 
129 //Brown-out Reset Voltage bits
130 //1
131 //2
132 //3 Minimum setting
133 //0 Maximum setting
134 #pragma config BORV = 0
135 
136 //Power-up Timer Enable bit
137 //OFF PWRT disabled
138 //ON PWRT enabled
139 #pragma config PWRT = ON
140 
141 
142 //******************************************************************************
143 // Register: CCONFIG2H @ 0x300003
144 //******************************************************************************
145 
146 //Watchdog Timer Postscale Select bits
147 //8 1:8
148 //1 1:1
149 //32768 1:32768
150 //1024 1:1024
151 //2 1:2
152 //32 1:32
153 //16 1:16
154 //16384 1:16384
155 //128 1:128
156 //4096 1:4096
157 //64 1:64
158 //8192 1:8192
159 //2048 1:2048
160 //512 1:512
161 //256 1:256
162 //4 1:4
163 #pragma config WDTPS = 1
164 
165 //Watchdog Timer Enable bit
166 //OFF WDT disabled (control is placed on the SWDTEN bit)
167 //ON WDT enabled
168 #pragma config WDT = OFF
169 
170 
171 //******************************************************************************
172 // Register: CONFIG3H @ 0x300005
173 //******************************************************************************
174 
175 //CCP2 MUX bit
176 //OFF CCP2 input/output is multiplexed with RB3
177 //ON CCP2 input/output is multiplexed with RC1
178 #pragma config CCP2MX = OFF
179 
180 //PORTB A/D Enable bit
181 //OFF PORTB<4:0> pins are configured as digital I/O on Reset
182 //ON PORTB<4:0> pins are configured as analog input channels on Reset
183 #pragma config PBADEN = OFF
184 
185 //Low-Power Timer 1 Oscillator Enable bit
186 //OFF Timer1 configured for higher power operation
187 //ON Timer1 configured for low-power operation
188 #pragma config LPT1OSC = OFF
189 
190 //MCLR Pin Enable bit
191 //OFF RE3 input pin enabled; MCLR pin disabled
192 //ON MCLR pin enabled; RE3 input pin disabled
193 #pragma config MCLRE = ON
194 
195 
196 //******************************************************************************
197 // Register: CONFIG4L @ 0x300006
198 //******************************************************************************
199 
200 //Background Debugger Enable bit
201 //OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
202 //ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
203 #pragma config DEBUG = OFF
204 
205 //Stack Full/Underflow Reset Enable bit
206 //OFF Stack full/underflow will not cause Reset
207 //ON Stack full/underflow will cause Reset
208 #pragma config STVREN = ON
209 
210 //Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit
211 //OFF ICPORT disabled
212 //ON ICPORT enabled
213 #pragma config ICPRT = OFF
214 
215 //Extended Instruction Set Enable bit
216 //OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
217 //ON Instruction set extension and Indexed Addressing mode enabled
218 #pragma config XINST = OFF
219 
220 //Single-Supply ICSP Enable bit
221 //OFF Single-Supply ICSP disabled
222 //ON Single-Supply ICSP enabled
223 #pragma config LVP = OFF
224 
225 
226 //******************************************************************************
227 // Register: CONFIG5L @ 0x300008
228 //******************************************************************************
229 
230 //Code Protection bit
231 //OFF Block 0 (000800-001FFFh) is not code-protected
232 //ON Block 0 (000800-001FFFh) is code-protected
233 #pragma config CP0 = OFF
234 
235 
236 //Code Protection bit
237 //OFF Block 1 (002000-003FFFh) is not code-protected
238 //ON Block 1 (002000-003FFFh) is code-protected
239 #pragma config CP1 = OFF
240 
241 //Code Protection bit
242 //OFF Block 2 (004000-005FFFh) is not code-protected
243 //ON Block 2 (004000-005FFFh) is code-protected
244 #pragma config CP2 = OFF
245 
246 //Code Protection bit
247 //OFF Block 3 (006000-007FFFh) is not code-protected
248 //ON Block 3 (006000-007FFFh) is code-protected
249 #pragma config CP3 = OFF
250 
251 
252 //******************************************************************************
253 // Register: CONFIG5H @ 0x300009
254 //******************************************************************************
255 
256 //Data EEPROM Code Protection bit
257 //OFF Data EEPROM is not code-protected
258 //ON Data EEPROM is code-protected
259 #pragma config CPD = OFF
260 
261 //Boot Block Code Protection bit
262 //OFF Boot block (000000-0007FFh) is not code-protected
263 //ON Boot block (000000-0007FFh) is code-protected
264 #pragma config CPB = OFF
265 
266 
267 //******************************************************************************
268 // Register: CONFIG6L @ 0x30000A
269 //******************************************************************************
270 
271 //Write Protection bit
272 //OFF Block 0 (000800-001FFFh) is not write-protected
273 //ON Block 0 (000800-001FFFh) is write-protected
274 #pragma config WRT0 = OFF
275 
276 //Write Protection bit
277 //OFF Block 1 (002000-003FFFh) is not write-protected
278 //ON Block 1 (002000-003FFFh) is write-protected
279 #pragma config WRT1 = OFF
280 
281 //Write Protection bit
282 //OFF Block 2 (004000-005FFFh) is not write-protected
283 //ON Block 2 (004000-005FFFh) is write-protected
284 #pragma config WRT2 = OFF
285 
286 //Write Protection bit
287 //OFF Block 3 (006000-007FFFh) is not write-protected
288 //ON Block 3 (006000-007FFFh) is write-protected
289 #pragma config WRT3 = OFF
290 
291 
292 //******************************************************************************
293 // Register: CONFIG6H @ 0x30000B
294 //******************************************************************************
295 
296 //Boot Block Write Protection bit
297 //OFF Boot block (000000-0007FFh) is not write-protected
298 //ON Boot block (000000-0007FFh) is write-protected
299 #pragma config WRTB = OFF
300 
301 //Configuration Register Write Protection bit
302 //OFF Configuration registers (300000-3000FFh) are not write-protected
303 //ON Configuration registers (300000-3000FFh) are write-protected
304 #pragma config WRTC = OFF
305 
306 //Data EEPROM Write Protection bit
307 //OFF Data EEPROM is not write-protected
308 //ON Data EEPROM is write-protected
309 #pragma config WRTD = OFF
310 
311 
312 //******************************************************************************
313 // Register: CONFIG7L @ 0x30000C
314 //******************************************************************************
315 
316 //Table Read Protection bit
317 //OFF Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
318 //ON Block 0 (000800-001FFFh) is protected from table reads executed in other blocks
319 #pragma config EBTR0 = OFF
320 
321 //Table Read Protection bit
322 //OFF Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
323 //ON Block 1 (002000-003FFFh) is protected from table reads executed in other blocks
324 #pragma config EBTR1 = OFF
325 
326 //Table Read Protection bit
327 //OFF Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
328 //ON Block 2 (004000-005FFFh) is protected from table reads executed in other blocks
329 #pragma config EBTR2 = OFF
330 
331 //Table Read Protection bit
332 //OFF Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
333 //ON Block 3 (006000-007FFFh) is protected from table reads executed in other blocks
334 #pragma config EBTR3 = OFF
335 
336 
337 //******************************************************************************
338 // Register: CONFIG7H @ 0x30000D
339 //******************************************************************************
340 
341 //Boot Block Table Read Protection bit
342 //OFF Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
343 //ON Boot block (000000-0007FFh) is protected from table reads executed in other blocks
344 #pragma config EBTRB = OFF
345 
346 
347 #endif