PIC18 LaurTec Library
3.2.0
Open Source C Library for PIC18 Microcontrollers based on C18 - XC8 Compilers
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PIC18F14K50_config.h
Go to the documentation of this file.
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/*******************************************************************************
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Author : Mauro Laurenti
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Version : 1.0
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Created on Date : 19/06/2013
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Last update : 19/06/2013
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CopyRight 2006-2013 all rights are reserved
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********************************************************
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SOFTWARE LICENSE AGREEMENT
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********************************************************
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The usage of the supplied software imply the acceptance of the following license.
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The software supplied herewith by Mauro Laurenti (the Author)
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is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
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The software is owned by the Author, and is protected under applicable copyright laws.
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All rights are reserved.
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Any use in violation of the foregoing restrictions may subject the
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user to criminal sanctions under applicable laws (Italian or International ones), as well as to
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civil liability for the breach of the terms and conditions of this license.
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Commercial use is forbidden without a written acknowledgement with the Author.
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Personal or educational use is allowed if the application containing the following
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software doesn't aim to commercial use or monetary earning of any kind.
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THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
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WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
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TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
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IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
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CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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********************************************************
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PURPOSES
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********************************************************
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This file contains all the configuration words needed for the PIC18F14K50.
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It can be easily adapted to other PICs according to the available configurations.
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****** WARNING ******
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The configurations must be changed to reflect the application needs!
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*****************************************************************************/
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#ifndef PIC18F14K50_CONFIG_H
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#define PIC18F14K50_CONFIG_H
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#ifdef __XC8
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#include <xc.h>
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#endif
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//******************************************************************************
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// Register: CONFIG1L @ 0x300000
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//******************************************************************************
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// System Clock Postscaler Selection bits
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//CLKDIV2 CPU System Clock divided by 2
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//CLKDIV3 CPU System Clock divided by 3
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//NOCLKDIV No CPU System Clock divide
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//CLKDIV4 CPU System Clock divided by 4
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#pragma config CPUDIV = NOCLKDIV
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//USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
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//OFF USB clock comes directly from the OSC1/OSC2 oscillator block; no divide
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//ON USB clock comes from the OSC1/OSC2 divided by 2
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#pragma config USBDIV = OFF
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//******************************************************************************
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// Register: CONFIG1H @ 0x300001
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//******************************************************************************
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//Internal/External Oscillator Switchover bit
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//OFF Oscillator Switchover mode disabled
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//ON Oscillator Switchover mode enabled
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#pragma config IESO = OFF
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//PLLEN = 4 X PLL Enable bit
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//OFF PLL is under software control
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//ON Oscillator multiplied by 4
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#pragma config PLLEN = ON
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//Oscillator Selection bits
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//ECM EC (medium)
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//ERCCLKOUT External RC oscillator, CLKOUT function on OSC2
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//ECCLKOUTH EC, CLKOUT function on OSC2 (high)
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//XT XT oscillator
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//LP LP oscillator
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//ECCLKOUTL EC, CLKOUT function on OSC2 (low)
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//IRC Internal RC oscillator
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//ECCLKOUTM EC, CLKOUT function on OSC2 (medium)
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//IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2
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//ECH EC (high)
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//ECL EC (low)
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//ERC External RC oscillator
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//HS HS oscillator
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#pragma config FOSC = HS
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//Fail-Safe Clock Monitor Enable bit
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//OFF Fail-Safe Clock Monitor disabled
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//ON Fail-Safe Clock Monitor enabled
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#pragma config FCMEN = OFF
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//PCLKEN = Primary Clock Enable bit
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//OFF Primary clock is under software control
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//ON Primary clock enabled
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#pragma config PCLKEN = ON
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//******************************************************************************
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// Register: CONFIG2L @ 0x300002
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//******************************************************************************
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//Brown-out Reset Enable bits
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//NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
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//OFF Brown-out Reset disabled in hardware and software
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//ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
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#pragma config BOREN = OFF
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//Brown-out Reset Voltage bits
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//19 VBOR set to 1.9 V nominal
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//27 VBOR set to 2.7 V nominal
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//22 VBOR set to 2.2 V nominal
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//30 VBOR set to 3.0 V nominal
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#pragma config BORV = 30
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//PWRTEN = Power-up Timer Enable bit
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//OFF PWRT disabled
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//ON PWRT enabled
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#pragma config PWRTEN = OFF
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//******************************************************************************
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// Register: CCONFIG2H @ 0x300003
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//******************************************************************************
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//Watchdog Timer Postscale Select bits
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//8 1:8
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//1 1:1
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//32768 1:32768
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//1024 1:1024
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//2 1:2
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//32 1:32
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//16 1:16
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//16384 1:16384
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//128 1:128
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//4096 1:4096
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//64 1:64
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//8192 1:8192
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//2048 1:2048
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//512 1:512
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//256 1:256
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//4 1:4
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#pragma config WDTPS = 32768
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//Watchdog Timer Enable bit
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//OFF WDT is controlled by SWDTEN bit of the WDTCON register
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//ON WDT is always enabled. SWDTEN bit has no effect.
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#pragma config WDTEN = OFF
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//******************************************************************************
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// Register: CONFIG3H @ 0x300005
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//******************************************************************************
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//MCLR Pin Enable bit
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//OFF RA3 input pin enabled; MCLR pin disabled
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//ON MCLR pin enabled; RA3 input pin disabled
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#pragma config MCLRE = OFF
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//HFOFST = HFINTOSC Fast Start-up bit
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//OFF The system clock is held off until the HFINTOSC is stable.
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//ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
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#pragma config HFOFST = OFF
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//******************************************************************************
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// Register: CONFIG4L @ 0x300006
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//******************************************************************************
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//Background Debugger Enable bit
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//OFF Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins
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//ON Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug
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#pragma config DEBUG = OFF
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//Stack Full/Underflow Reset Enable bit
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//OFF Stack full/underflow will not cause Reset
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//ON Stack full/underflow will cause Reset
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#pragma config STVREN = ON
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//Extended Instruction Set Enable bit
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//OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
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//ON Instruction set extension and Indexed Addressing mode enabled
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#pragma config XINST = OFF
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//BBSIZ = Boot Block Size Select bit
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//OFF 1kW boot block size
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//ON 2kW boot block size
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#pragma config BBSIZ = OFF
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//Single-Supply ICSP Enable bit
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//OFF Single-Supply ICSP disabled
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//ON Single-Supply ICSP enabled
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#pragma config LVP = OFF
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//******************************************************************************
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// Register: CONFIG5L @ 0x300008
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//******************************************************************************
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//Code Protection bit
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//OFF Block 0 is not code-protected
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//ON Block 0 is code-protected
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#pragma config CP0 = OFF
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//Code Protection bit
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//OFF Block 1 is not code-protected
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//ON Block 1 is code-protected
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#pragma config CP1 = OFF
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//******************************************************************************
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// Register: CONFIG5H @ 0x300009
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//******************************************************************************
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//Data EEPROM Code Protection bit
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//OFF Data EEPROM is not code-protected
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//ON Data EEPROM is code-protected
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#pragma config CPD = OFF
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//Boot Block Code Protection bit
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//OFF Boot block is not code-protected
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//ON Boot block is code-protected
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#pragma config CPB = OFF
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//******************************************************************************
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// Register: CONFIG6L @ 0x30000A
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//******************************************************************************
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//Write Protection bit
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//OFF Block 0 is not write-protected
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//ON Block 0 is write-protected
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#pragma config WRT0 = OFF
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//Write Protection bit
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//OFF Block 1 is not write-protected
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//ON Block 1 is write-protected
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#pragma config WRT1 = OFF
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//******************************************************************************
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// Register: CONFIG6H @ 0x30000B
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//******************************************************************************
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//Boot Block Write Protection bit
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//OFF Boot block is not write-protected
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//ON Boot block is write-protected
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#pragma config WRTB = OFF
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//Configuration Register Write Protection bit
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//OFF Configuration registers are not write-protected
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//ON Configuration registers are write-protected
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#pragma config WRTC = OFF
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//Data EEPROM Write Protection bit
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//OFF Data EEPROM is not write-protected
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//ON Data EEPROM is write-protected
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#pragma config WRTD = OFF
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//******************************************************************************
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// Register: CONFIG7L @ 0x30000C
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//******************************************************************************
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//Table Read Protection bit
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//OFF Block 0 is not protected from table reads executed in other blocks
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//ON Block 0 is protected from table reads executed in other blocks
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#pragma config EBTR0 = OFF
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//Table Read Protection bit
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//OFF Block 1 is not protected from table reads executed in other blocks
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//ON Block 1 is protected from table reads executed in other blocks
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#pragma config EBTR1 = OFF
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//******************************************************************************
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// Register: CONFIG7H @ 0x30000D
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//******************************************************************************
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//Boot Block Table Read Protection bit
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//OFF Boot block is not protected from table reads executed in other blocks
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//ON Boot block is protected from table reads executed in other blocks
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#pragma config EBTRB = OFF
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#endif
LaurTec_PIC_libraries_v_3.2.0
conf
PIC18F14K50_config.h
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