PIC18 LaurTec Library  3.2.0
Open Source C Library for PIC18 Microcontrollers based on C18 - XC8 Compilers
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PIC18F2331_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.0
5 Created on Date : 30/04/2013
6 Last update : 30/04/2013
7 
8 CopyRight 2006-2013 all rights are reserved
9 
10 
11 ********************************************************
12 SOFTWARE LICENSE AGREEMENT
13 ********************************************************
14 
15 The usage of the supplied software imply the acceptance of the following license.
16 
17 The software supplied herewith by Mauro Laurenti (the Author) is intended for
18 use solely and exclusively on Microchip PIC Microcontroller (registered mark).
19 The software is owned by the Author, and is protected under applicable
20 copyright laws. All rights are reserved.
21 Any use in violation of the foregoing restrictions may subject the
22 user to criminal sanctions under applicable laws, as well as to civil liability
23 for the breach of the terms and conditions of this license.
24 Commercial use is forbidden without a written acknowledgement with the Author.
25 Personal or educational use is allowed if the application containing the
26 following software doesn't aim to commercial use or monetary earning of any kind.
27 
28 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
29 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
30 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
31 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
32 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
33 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
34 
35 
36 ********************************************************
37 PURPOSES
38 ********************************************************
39 
40 This file contains all the configuration words needed for the PIC18F2331.
41 It can be easily adapted to other PICs according to the available configurations.
42 
43 ****** WARNING ******
44 
45 The configurations must be changed to reflect the application needs!
46 
47 *****************************************************************************/
48 
49 
50 #ifndef PIC18F2331_CONFIG_H
51 #define PIC18F2331_CONFIG_H
52 
53 #ifdef __XC8
54 #include <xc.h>
55 #endif
56 
57 
58 //******************************************************************************
59 // Register: CONFIG1H @ 0x300001
60 //******************************************************************************
61 
62 //Internal External Oscillator Switchover bit
63 //OFF Internal External Switchover mode disabled
64 //ON Internal External Switchover mode enabled
65 #pragma config IESO = OFF
66 
67 //Oscillator Selection bits
68 //RC 11XX External RC oscillator, CLKO function on RA6
69 //RC1 101X External RC oscillator, CLKO function on RA6
70 //IRCIO Internal oscillator block, port function on RA6 and port function on RA7
71 //RCIO External RC oscillator, port function on RA6
72 //RC2 External RC oscillator, CLKO function on RA6
73 //XT XT oscillator
74 //LP LP oscillator
75 //IRC Internal oscillator block, CLKO function on RA6 and port function on RA7
76 //HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
77 //ECIO EC oscillator, port function on RA6
78 //EC EC oscillator, CLKO function on RA6
79 //HS HS oscillator
80 #pragma config OSC = IRC
81 
82 //Fail-Safe Clock Monitor Enable bit
83 //OFF Fail-Safe Clock Monitor disabled
84 //ON Fail-Safe Clock Monitor enabled
85 #pragma config FCMEN = OFF
86 
87 
88 //******************************************************************************
89 // Register: CONFIG2L @ 0x300002
90 //******************************************************************************
91 
92 //Brown-out Reset Enable bits
93 //OFF Brown-out Reset disabled
94 //ON Brown-out Reset enabled
95 #pragma config BOREN = ON
96 
97 //Brown Out Reset Voltage bits
98 //42 VBOR set to 4.2V
99 //27 VBOR set to 2.7V
100 //45 VBOR set to 4.5V
101 #pragma config BORV = 42
102 
103 //Power-up Timer Enable bit
104 //OFF PWRT disabled
105 //ON PWRT enabled
106 #pragma config PWRTEN = ON
107 
108 
109 //******************************************************************************
110 // Register: CONFIG2H @ 0x300003
111 //******************************************************************************
112 
113 //Watchdog Timer Postscale Select bits
114 //8 1:8
115 //1 1:1
116 //32768 1:32768
117 //1024 1:1024
118 //2 1:2
119 //32 1:32
120 //16 1:16
121 //16384 1:16384
122 //128 1:128
123 //4096 1:4096
124 //64 1:64
125 //8192 1:8192
126 //2048 1:2048
127 //512 1:512
128 //256 1:256
129 //4 1:4
130 #pragma config WDPS = 1
131 
132 //Watchdog Timer Enable bit
133 //OFF WDT disabled (control is placed on the SWDTEN bit)
134 //ON WDT enabled
135 //WINEN = Watchdog Timer Window Enable bit
136 //OFF WDT window disabled
137 //ON WDT window enabledbled
138 #pragma config WDTEN = OFF
139 
140 
141 //******************************************************************************
142 // Register: CONFIG3L @ 0x300004
143 //******************************************************************************
144 
145 //Timer1 Oscillator MUX
146 //OFF Standard (legacy) Timer1 oscillator operation
147 //ON Low-power Timer1 operation when microcontroller is in Sleep mode
148 #pragma config T1OSCMX = OFF
149 
150 //PWM output pins Reset state control
151 //OFF PWM outputs disabled upon Reset (default)
152 //ON PWM outputs drive active states upon Reset
153 #pragma config PWMPIN = OFF
154 
155 //High-Side Transistors Polarity
156 //HIGH PWM1, 3, 5 and 7 are active-high
157 //LOW PWM1, 3, 5 and 7 are active-low
158 #pragma config HPOL = HIGH
159 
160 //Low-Side Transistors Polarity
161 //HIGH PWM0, 2, 4 and 6 are active-high
162 //LOW PWM0, 2, 4 and 6 are active-low
163 #pragma config LPOL = LOW
164 
165 
166 //******************************************************************************
167 // Register: CONFIG3H @ 0x300005
168 //******************************************************************************
169 
170 //MCLR Pin Enable bit
171 //OFF Disabled
172 //ON Enabled
173 #pragma config MCLRE = ON
174 
175 
176 //******************************************************************************
177 // Register: CONFIG4L @ 0x300006
178 //******************************************************************************
179 
180 //Background Debugger Enable bit
181 //OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
182 //ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
183 #pragma config DEBUG = ON
184 
185 //Stack Full/Underflow Reset Enable bit
186 //OFF Stack full/underflow will not cause Reset
187 //ON Stack full/underflow will cause Reset
188 #pragma config STVREN = ON
189 
190 //Low-Voltage ICSP Enable bit
191 //OFF Low-voltage ICSP disabled
192 //ON Low-voltage ICSP enabled
193 #pragma config LVP = OFF
194 
195 
196 //******************************************************************************
197 // Register: CONFIG5L @ 0x300008
198 //******************************************************************************
199 
200 //Code Protection bit
201 //OFF Block 0 (000200-000FFFh) not code-protected
202 //ON Block 0 (000200-000FFFh) code-protected
203 #pragma config CP0 = OFF
204 
205 //Code Protection bit
206 //OFF Block 1 (001000-001FFF) not code-protected
207 //ON Block 1 (001000-001FFF) code-protected
208 #pragma config CP1 = OFF
209 
210 
211 //******************************************************************************
212 // Register: CONFIG5H @ 0x300009
213 //******************************************************************************
214 
215 //Data EEPROM Code Protection bit
216 //OFF Data EEPROM not code-protected
217 //ON Data EEPROM code-protected
218 #pragma config CPD = OFF
219 
220 //Boot Block Code Protection bit
221 //OFF Boot Block (000000-0001FFh) not code-protected
222 //ON Boot Block (000000-0001FFh) code-protected
223 #pragma config CPB = OFF
224 
225 
226 //******************************************************************************
227 // Register: CONFIG6L @ 0x30000A
228 //******************************************************************************
229 
230 //Write Protection bit
231 //OFF Block 0 (000200-000FFFh) not write-protected
232 //ON Block 0 (000200-000FFFh) write-protected
233 #pragma config WRT0 = OFF
234 
235 //Write Protection bit
236 //OFF Block 1 (001000-001FFF) not write-protected
237 //ON Block 1 (001000-001FFF) write-protected
238 #pragma config WRT1 = OFF
239 
240 
241 //******************************************************************************
242 // Register: CONFIG6H @ 0x30000B
243 //******************************************************************************
244 
245 //Boot Block Write Protection bit
246 //OFF Boot Block (000000-0001FFh) not write-protected
247 //ON Boot Block (000000-0001FFh) write-protected
248 #pragma config WRTB = OFF
249 
250 //Configuration Register Write Protection bit
251 //OFF Configuration registers (300000-3000FFh) not write-protected
252 //ON Configuration registers (300000-3000FFh) write-protected
253 #pragma config WRTC = OFF
254 
255 //Data EEPROM Write Protection bit
256 //OFF Data EEPROM not write-protected
257 //ON Data EEPROM write-protected
258 #pragma config WRTD = OFF
259 
260 
261 //******************************************************************************
262 // Register: CONFIG7L @ 0x30000C
263 //******************************************************************************
264 
265 //Table Read Protection bit
266 //OFF Block 0 (000200-000FFFh) not protected from table reads executed in other blocks
267 //ON Block 0 (000200-000FFFh) protected from table reads executed in other blocks
268 #pragma config EBTR0 = OFF
269 
270 //Table Read Protection bit
271 //OFF Block 1 (001000-001FFF) not protected from table reads executed in other blocks
272 //ON Block 1 (001000-001FFF) protected from table reads executed in other blocks
273 #pragma config EBTR1 = OFF
274 
275 
276 //******************************************************************************
277 // Register: CONFIG7H @ 0x30000D
278 //******************************************************************************
279 //Boot Block Table Read Protection bit
280 //OFF Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
281 //ON Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
282 //Register: IDLOC0 @ 0x200000
283 //Register: IDLOC1 @ 0x200001
284 //Register: IDLOC2 @ 0x200002
285 //Register: IDLOC3 @ 0x200003
286 //Register: IDLOC4 @ 0x200004
287 //Register: IDLOC5 @ 0x200005
288 //Register: IDLOC6 @ 0x200006
289 //Register: IDLOC7 @ 0x200007
290 #pragma config EBTRB = OFF
291 
292 #endif